Non-planar structures such as finFETs are being implemented in integrated circuit fabrication at the fourteen nanometer technology node. One important challenge with the implementation of non-planar structures is the formation of contacts to the non-planar (fin) source/drain regions. There are two approaches for contact formation: formation of contacts to merged fins and formation of contacts to unmerged fins.
For merged fins, a layer of epitaxial silicon is grown on fins. As a result of the epitaxial growth, adjacent fins become merged. The resulting contact area is large and lacks topographical variation. Therefore, conventional silicide processes can be used to successfully form silicide contacts to the top surface of the merged fins. Conventional silicide processes include the formation of an intermetallic silicide material on the active silicon. Current fabrication processes typically use nickel-platinum silicide (NiPtSi), nickel silicide (NiSi) or titanium silicide (TiSi) as the silicide material.
Unmerged fins are required, for example, for Static Random Access Memory (SRAM) devices. Unmerged fins permit the design of SRAM cells with tighter pitch, taking less area of the Si for the SRAM and making the overall chip layout smaller. Typically, SRAM cells are large in today's integrated circuits. It is well known that interface resistivity (Rs) is a significant factor in the overall contact resistance of an integrated circuit. A plurality of unmerged fins provides a large number of small contacts, each of which adds resistance. The total of the resistance from the contacts can be significantly larger than that of a merged set of fins, which has a large contact area and lower resistance. Lowering the contact resistance of the many small unmerged fins can make a significant difference in circuit performance. However, contacting unmerged fins let alone in a manner with low contact resistance is particularly challenging. For example, for finFETs at the ten nanometer technology node, the fins are extremely narrow and the use of silicidation to form contacts risks the complete consumption of the fin by the silicide reaction.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with silicide contacts on unmerged non-planar transistors. In addition, it is desirable to provide integrated circuits and methods for fabricating integrated circuits which provide for contact formation on sidewalls of non-planar structures. Also, it is desirable to provide integrated circuits and methods for fabricating integrated circuits which consumes a low amount of silicon of a non-planar structure to avoid complete consumption of the non-planar structure during contact formation through silicidation. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.